A conventional technology has been disclosed where a multi-core processor system is formed by equipping multiple central processing units (CPUs) to a computer system. In the multi-core processor system, parallel processing is enabled by assigning software to the CPUs via a function of an operating system (OS).
A technology has been disclosed as a resource control method for a multi-core processor system reduces power consumption of contents whose calculation densities are low by dynamically increasing or decreasing the calculation capacity of the CPUs using statistical information based on historical load properties of specific processes (see, e.g., Japanese Laid-Open Patent Publication No. 2009-501482). A technology has been disclosed according to which a hardware performance counter is attached to a multi-core processor system to dynamically analyze the amount of load and when the amount of load counted does not reach the performance set in advance, necessary hardware resources are enhanced (see, e.g., Japanese Laid-Open Patent Publication No. 2009-521056).
In a multi-core processor system, access contention occurs consequent to simultaneous access of shared memory by the multiple cores and the performance of the system is degraded. A technology has been disclosed according to which, when access contention for the memory occurs, a low-speed clock is supplied to CPUs that do not so frequently access the memory and thereby, the throughput is improved of each of the CPUs that frequently access the memory (see, e.g., Japanese Laid-Open Patent Publication No. H11-110363).
However, among the conventional techniques, a problem arises with the technology according to Japanese Laid-Open Patent Publication No. 2009-501482 in that no statistical value is collected for a device by which arbitrary operations are executed by the user thereof. For example, for a system having multiple applications, each started up at an arbitrary timing by the user, a problem arises in that combinations of applications are tremendous and storage of statistical information therefore is impractical.
In the technology according to Japanese Laid-Open Patent Publication No. 2009-521056, the occurrence of contention with access to the memory is coped with by increasing the speed of the clock of the delayed CPUs or by increasing the clock of the memory. A problem arises with these methods of coping with contention in that not only the power consumption is increased but also the problem on the performance of the memory caused by the access contention remains unsolved by merely increasing the clocks. Another problem also arises for a large-scale system-on-a-chip (SoC) in that it is difficult to determine where the performance counter is to be disposed. Meanwhile, yet another problem arises in that the scale of the system is increased when performance counters are disposed at all the possible points such as at CPUs and buses.
A problem arises with the technology according to Japanese Laid-Open Patent Publication No. H11-110363 in that the decreasing of the speed of the CPUs not so frequently accessing the memory also influences applications that operate in the space on a cache memory and whose speeds do not need to be decreased.
In a heterogeneous multi-core processor system that is an asymmetrical multi-core processor system, the loads on the CPUs are imbalanced due to the property of asymmetry and therefore, a problem arises in that wasteful utilization of the CPU resource occurs.